A Parallel Processing Architecture for HDTV Encoding System

We propose a parallel processing architecture to encode HDTV(High Definition TV) signals by dividing input signals into several sub-pictures. Each sub-picture is encoded in parallel by a sub-picture encoding module(SEM) which has the capability to encode video signals according to MPEG-2 MP@ML(Main Profile at Main Level) specification. Each SEM consists of application specific integrated circuits(ASIC) we developed. The bit streams generated by sub-picture encoding modules are assembled into a single bit stream complying with the MPEG-2 MP@HL(Main Profile at High Level) specification. We also present a rate control scheme for parallel encoding.

Published

1996-10

Content type

Original Research

Keywords

SDTV, HDTV, MPEG

DOI

10.5594/M001244

ISBN

978-1-61482-947-8