Parallel Processing Solves the DTV Format Conversion Problem

The FCC mandate to broadcast Digital Television (DTV) has forced broadcasters to face the challenge of integrating High Definition Television (HDTV) programming into their NTSC or 601 plants. In the early stages of the DTV rollout, broadcasters will be required to simultaneously broadcast program material on both digital and analog channels (simulcast). In addition, broadcasters will need to combine locally generated advertising, programming and logos with network generated programming. However, this material will now be in a variety of different high definition and standard definition formats. This will force the broadcaster to convert most of their material from standard definition to high definition (up-convert), from high definition to standard definition (down-convert), or from one high definition format to another (side-convert). Often all of these conversions will need to be performed simultaneously. This has created an instant need for a variety of format converters. — The typical approach to format conversion is to “hard–wire” the processing algorithms using Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs). This approach has several disadvantages such as limited adaptability to new formats and lack of expandability to higher complexity processing algorithms. This paper describes an alternative approach using massively parallel computer technology to create a fully programmable video processor. This “Video Computer” can be programmed to perform a variety of video processing functions and provides the flexibility and scalability to support emerging formats and expanded capabilities without requiring a system redesign.

Published

1999-02

Content type

Original Research

DOI

10.5594/M00941

ISBN

978-1-61482-930-0