A Design Approach to Creating Scalable Beyond-4K Video Processing Systems on FPGAs

An unquenchable end-user thirst for enhanced video quality results in an ever-scaling video frame size and frame rate requirements. As we move from 4K to 8K and 120fps to 300fps, inevitably the computational complexity of video processing systems required to consume, process and deliver video content increases. The need for solutions to support combinations of frame sizes and rates, as well as future increments, emphasizes the need for system scalability. The computational complexity and scalability requirements pose exciting challenges for FPGA implementation of video processing pipelines. This paper presents implementation techniques and methodologies to overcome these challenges. We specifically concentrate on architectures whereby the input per-pixel video sample rate exceeds the system clock rate. Novel results include classifying pixel processing orders and presenting a component-based design approach for future-proofing video processing solutions against an ever-scaling computational complexity requirement. Resource and memory bandwidth requirements of such systems are also analysed and trends presented.

Published

2013-10

Content type

Original Research

Keywords

FPGA, video processing, 4K

DOI

10.5594/M001527

ISBN

978-1-61482-953-9