A New Programming Methodology for Rapid Deployment of Computationally Intensive Broadcast Codecs

Higher quality video encode is only one of many requirements in an industry increasingly interested in lower power consumption, upgradable standards flexibility, and lower cost. To date, meeting all needs at the same time has been unachievable, limited by inefficiencies in underlying silicon architectures and traditional programming methodologies. Legacy processing solutions using arrays of FPGAs, DSPs, GPPs or inflexible ASICs have forced designers to make feature set tradeoffs and solutions that do not scale well with increasing pixel rates. A new approach using a dataflow programming methodology and a massively parallel processor array introduces a technical discontinuity in meeting tomorrow's equipment requirement with respect to computationally intensive algorithms such as H.264 Hi10P, Level 4.1 or greater. This development flow allows for 1) rapid deployment 2) software defined implementation that is upgradable for new features or algorithm enhancements, 3) high quality/low power video encode at the point of capture. We present two key components of a H.264 encoder, CABAC and motion estimation, and demonstrate the application of the dataflow methodology on a massively parallel processor.

Published

2010-10

Content type

Original Research

Keywords

Dataflow programming, massively parallel architecture, H.264 codec, low power

DOI

10.5594/M001387

ISBN

978-1-61482-944-7