Considerations When Designing for the 3Gbps SDI Interface

When SMPTE 424M came out with the standard for a 3 Gbps Serial Digital Interface, much of what was standardized was similar to the HD SDI interface that is so well established and understood. The assumption of many early adopters of this standard was that you could use the same architectures to build 3 Gbps equipment as what had been used for HD SDI, and then build studios with this equipment in order to support the higher definition formats. Unfortunately when SMPTE 424M was approved, it included a relaxed jitter specification, allowing up to 0.3UI of alignment jitter rather than the 0.2UI which is permitted in SMPTE 292M - the HD SDI specification. This paper explores the consequences of this relaxed specification on system performance and looks at new architectures for studio equipment which are able to better tolerate the increased jitter, as well as discussing the fact that studio designers may want to look more closely at some performance measures of 3 Gbps equipment rather than just looking for ‘SMPTE 424M Compliant’

Published

2008-10

Content type

Original Research

DOI

10.5594/M001023

ISBN

978-1-61482-939-3