Architecture and VLSI Implementation of the MPEG-2:MP@ML Video Decoding Process

This paper describes a recently developed silicon component that efficiently implements real-time decompression of an MPEG-2 encoded video data stream. The chip has been developed by IBM Corp. and is fully compliant with the MPEG-2 Draft Standard at MP@ML (Main Profile at Main Level). An overview of the MPEG-2 algorithm is presented, and the main characteristics of the video decoder chip are outlined. The descriptions and examples of particular internal coprocessors are given in terms of function and specific application environments.

Print ISSN

0036-1682

Published

1995-02

Content type

Original Research

DOI

10.5594/J04708