A High-Speed Architecture for Image Computation

A system architecture well suited to the tasks of generating, manipulating, and processing digital images of arbitrary sample resolution is presented. The architecture reflects a series of design decisions made at various conceptual levels. These decisions and the general system requirements which underlie them are examined. The architecture is outlined in a top-down fashion proceeding from the system interface level to the macroscopic hardware level to the PC board level. The parallel software architectural development is also summarized. Finally, a specific application software system is discussed. The example, a rendering system, illustrates the multitasking multiple-processor nature of the system and suggests a method for handling dynamic load-balancing among the computational subsystems.

Print ISSN

0036-1682

Published

1988-06

Content type

Original Research

DOI

10.5594/J02943